package ChiselSoc

import ChiselSoc.ImemPortIo.WORD_LEN
import chisel3.util.experimental.loadMemoryFromFile
import chisel3._
import chisel3.stage.ChiselStage
import chisel3.util._

class Top extends Module{
  val io = IO(new Bundle{
    val exit = Output(Bool())
  })

  val core = Module(new Core())         //将Core这个module例化过来
  val memory = Module(new Memory())       //将memory这个module例化过来

  //将core和memory接口连接
  //将core中的exit测试结果连接到Top接口
  core.io.imem <> memory.io.imem
  io.exit := core.io.exit

}

object TopMain extends App {
  println("Generating the adder hardware")
  emitVerilog(new Top(), Array("--target-dir", "generated/ChiselSoc/Top"))
}
